Direct Answer
KiCad's DRC is a practical first-pass SMT assembly risk filter because it exposes clearance violations, footprint errors, and copper balance issues that directly cause solder bridges, tombstoning, and poor wetting during reflow. By tracking DRC error trends across board revisions, you can identify design maturity, prioritize fixes by real assembly impact, and share actionable data with your EMS partner before fabrication.
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Why DRC Trends Matter More Than a Single Error Count
Most engineers run KiCad DRC once, fix the errors, and move on. That approach misses the most valuable signal: the trend. A single DRC report tells you what is wrong right now. A series of DRC reports across revisions tells you whether your design is converging toward manufacturability or accumulating risk.
When you track DRC output from revision to revision, you can see three distinct patterns:
- Declining error counts indicate a maturing design. Clearance violations and footprint mismatches are being resolved systematically.
- Stable error counts suggest either acceptable residual risk or a design that has not been reviewed carefully. You need to classify what remains.
- Spiking error counts after a specific edit point directly trace to a design change. This traceability is invaluable when a new error appears after a footprint swap or a connector relocation.
For SMT assembly, the trend matters because it correlates with yield. A board that shows repeated clearance violations near fine-pitch components will likely produce solder bridges on the line. A board that consistently passes DRC with clean courtyard checks will place components without pick-and-place collisions. Tracking these trends over time gives you a quantitative maturity score that you can include in your RFQ package.
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Classifying DRC Errors by SMT Assembly Risk
Not all DRC flags carry the same weight on an SMT line. Treating a silkscreen overlap with the same severity as a BGA pad-to-pad clearance violation leads to poor prioritization. Classify your DRC output into three risk tiers.
High-Risk: Footprint and Land Pattern Errors
Footprint errors are the most direct path to assembly failure. KiCad DRC checks pad sizes, pad spacing, and courtyard definitions against your design rules. When these fail, the consequences appear during placement and reflow.
A pad that is too small for the component termination reduces solder paste contact area. This leads to poor wetting, weak solder joints, and potential opens after thermal cycling. A pad that is too large can cause tombstoning on small passive components because surface tension during reflow pulls one termination more than the other.
Check your footprint land patterns against IPC-7351. This standard defines land pattern dimensions for SMT components based on tolerance classes. If your KiCad library footprints were created manually rather than from an IPC-7351 generator, verify them against the standard before sending files to fabrication.
Medium-Risk: Clearance Violations
Clearance violations are the most common DRC errors, but their assembly impact varies widely by location.
A clearance violation between two BGA pads is critical. Solder paste will bridge during reflow, and the defect may not be visible from the outside. You will need X-ray inspection to detect it, which adds cost and time to the first-article inspection.
A clearance violation between a through-hole connector pad and an adjacent SMT pad is also serious. The solder wave or selective solder process can create solder balls or bridges in that gap.
However, a clearance violation between a mounting hole and a silkscreen label is cosmetic. It does not affect assembly, but it still needs correction for manufacturing documentation clarity.
Use this classification table to prioritize your DRC fixes:
| DRC Error Type | SMT Risk Level | Typical Assembly Failure | Inspection Method |
|---|---|---|---|
| BGA pad-to-pad clearance | High | Solder bridge, short | X-ray |
| Fine-pitch QFP pad clearance | High | Solder bridge, insufficient spacing | AOI, X-ray |
| Passive component pad size mismatch | High | Tombstoning, poor wetting | AOI, manual |
| Via-in-pad without plugging | Medium | Solder wicking, voiding | X-ray, cross-section |
| Copper pour to pad clearance | Medium | Thermal imbalance, tombstoning | AOI |
| Courtyard overlap | Medium | Pick-and-place collision | Visual, AOI |
| Silkscreen over pad | Low | Cosmetic, solder mask damage | Visual |
Low-Risk: Copper Balance and Thermal Issues
KiCad DRC can flag copper balance issues, especially on inner layers. These are not electrical errors, but they matter for SMT assembly because uneven copper distribution causes board warpage during reflow.
A board that warps during reflow will have components that do not sit flat on the solder paste. This creates opens, skewed placements, and solder joint stress. The problem is worse on larger boards and boards with asymmetric copper distribution between layers.
Copper balance is not a standard DRC check in all KiCad versions, but you can use the design rules checker to flag large copper areas on one layer without corresponding areas on the opposite layer. If your board is larger than 100 mm on any side, pay attention to copper balance. A 1.6 mm FR-4 board with 1 oz copper will warp noticeably if one side has a solid ground pour and the other has only traces.
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Practical Example: Evaluating a Mixed-Signal Board
Consider a 4-layer mixed-signal board with a 0.8 mm pitch QFP-64, several 0402 passives, and two BGA-49 packages. The stackup is 1.6 mm FR-4, 1 oz copper on outer layers, 0.5 oz on inner layers.
When you run KiCad DRC with assembly-specific rules, you get the following error classes:
- 12 clearance violations between 0402 pads and adjacent copper pours. These are medium risk because the copper pour acts as a heat sink, causing uneven reflow and potential tombstoning.
- 3 courtyard violations where the QFP-64 courtyard overlaps the BGA-49 courtyard. These are high risk because the pick-and-place nozzle may collide during placement.
- 1 footprint error on an 0402 resistor where the pad width is 0.1 mm smaller than the IPC-7351 recommendation. This is high risk for poor wetting.
Your DRC trend across three revisions shows the clearance violations dropping from 28 to 12, the courtyard violations appearing only after you moved the BGA package closer to the QFP, and the footprint error persisting from the original library.
The action plan is clear:
1. Fix the 0402 footprint immediately. Check the library against IPC-7351 and correct the pad width. 2. Move the BGA-49 away from the QFP-64 to resolve courtyard overlap. This is a placement change, not a routing change, so it is fast. 3. Add thermal relief spokes to the copper pours near the 0402 pads. This reduces the heat sink effect and improves reflow uniformity.
After these fixes, run DRC again. The trend should show zero high-risk errors and only a few low-risk silkscreen items. That is the point where you can confidently send the board to fabrication.
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Using DRC Output to Improve Your BOM and Centroid Data
DRC trends do more than catch layout errors. They also reveal problems in your BOM and centroid data that will cause assembly issues downstream.
When KiCad generates the centroid file for SMT placement, it uses the footprint origin and reference designator. If your footprint library has incorrect origins, the centroid file will be off by the same amount for every component using that footprint. This causes systematic placement errors on the line.
Review your DRC report for footprint origin warnings. KiCad can flag footprints where the origin is not at the component center. For small passives like 0402 and 0603, an origin offset of even 0.1 mm can cause the component to be placed off-pad, leading to poor wetting or tombstoning.
Your BOM also needs a DRC-style review. Check that every reference designator in the DRC report has a corresponding BOM entry. Missing BOM entries cause line stoppages during kitting. Duplicate reference designators cause placement errors. Both are detectable by cross-referencing your DRC output with your BOM.
Before sending files to your turnkey PCBA partner, verify these three data sets:
- Centroid file: Confirm X/Y coordinates, rotation, and layer for every SMT component.
- BOM: Confirm manufacturer part numbers, quantities, and reference designators match the layout.
- DRC report: Export the final report and include it with your fabrication and assembly files.
Sharing the DRC report with your EMS provider is not a sign of weakness. It is a professional practice that reduces first-article inspection time. The manufacturer can see which errors you knowingly accepted and which you resolved. This alignment prevents surprise findings during the design for manufacturability (DFM) review.
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Common Mistakes Engineers Make with KiCad DRC for SMT
Engineers repeat the same DRC mistakes across projects. Recognizing these patterns will help you avoid them.
Treating All DRC Errors as Equal
The most common mistake is treating every DRC flag with the same urgency. A silkscreen overlap and a BGA pad clearance violation are not comparable. The silkscreen error will not affect assembly. The BGA clearance violation will cause a short that requires X-ray inspection to find.
Use the risk classification table above to triage your DRC output. Fix high-risk errors first, medium-risk errors second, and low-risk errors last. If you run out of time, accept the low-risk errors and document them in your RFQ.
Ignoring Courtyard Violations
Courtyard violations are frequently dismissed because they do not affect electrical connectivity. But they directly affect SMT placement. The pick-and-place machine uses courtyard definitions to determine component spacing. If two courtyards overlap, the machine may collide components during placement, causing damage or misalignment.
Check courtyard violations carefully, especially near connectors, large BGAs, and components with tall profiles. A courtyard violation between a connector and a nearby capacitor can cause the capacitor to be knocked off during connector seating.
Running DRC with Stale Rules
KiCad DRC is only as good as the design rules you configure. If you use the default rules without adjusting for your assembly process, you will miss real risks.
Configure your DRC rules to match your manufacturer's capabilities. If your EMS partner uses a standard 0.15 mm solder mask expansion, set your clearance rules accordingly. If you use a 0.4 mm pitch BGA, set the pad-to-pad clearance to match the stencil design capability.
Forgetting to Run DRC After Final Changes
A common failure mode is running DRC early in the design, fixing errors, then making final component changes without re-running DRC. The final changes may introduce new violations that go undetected.
Make DRC a mandatory step in your release process. Run it after every significant edit, and especially after the final layout freeze. The trend data from these repeated runs is what gives you confidence in the design maturity.
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What to Include in Your RFQ to Help the Manufacturer Assess SMT Risk
Your RFQ package should give the manufacturer everything needed to assess assembly risk before the first board is built. A complete package reduces back-and-forth communication and speeds up the first-article inspection.
Include these items in your RFQ:
- KiCad DRC report: The final report with your design rules noted. This shows the manufacturer which errors you accepted and which you resolved.
- Design rules used: List the clearance, track width, via size, and solder mask expansion values you configured in KiCad.
- BOM with manufacturer part numbers: Include MPNs, not just generic descriptions. This allows the manufacturer to check component availability, moisture sensitivity, and package dimensions.
- Centroid file: The pick-and-place data with correct origins and rotations.
- Layer stackup: Specify the number of layers, copper weight, laminate material, and finished board thickness.
- Known exceptions: If you accepted a DRC error for a specific reason, document it. For example, a clearance violation near a high-voltage area may be intentional.
Mention moisture-sensitive components in your RFQ. Components rated per J-STD-020 with a moisture sensitivity level (MSL) of 3 or higher require special handling. The manufacturer needs to know this to plan baking and floor life management per J-STD-033.
Also mention any special reflow requirements. If you have a mixed-technology board with both through-hole and SMT components, the manufacturer may need a selective solder process after reflow. This affects stencil design and process planning.
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How DRC Trends Predict SMT Assembly Yield
DRC trends are a leading indicator of assembly yield. A design that shows decreasing high-risk errors across revisions will produce fewer defects on the line. A design with persistent or increasing errors will produce more.
The correlation works because DRC errors map directly to known assembly failure modes. Clearance violations cause solder bridges. Footprint errors cause tombstoning and poor wetting. Courtyard violations cause placement collisions. Copper imbalance causes warpage.
When you track these trends, you can predict which failure modes are most likely for your board. This allows you to plan inspection resources accordingly. If your trend shows persistent BGA clearance violations, plan for X-ray inspection on every BGA. If your trend shows clean fine-pitch clearances, AOI may be sufficient.
The trend data also helps you compare design alternatives. If you are choosing between two component placements, run DRC on both and compare the error profiles. The option with fewer high-risk errors is the better choice for assembly yield.
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When to Involve Your Manufacturer
You do not need to wait until your design is complete to involve your manufacturer. Early engagement on DRC trends can prevent costly redesigns.
Share your DRC trend data with your EMS provider when you have significant error counts or when you are making a major design change. The manufacturer can provide feedback on whether your accepted errors are actually acceptable for their process.
For example, a clearance violation that you consider acceptable may be problematic for a manufacturer using a specific stencil thickness or reflow profile. The manufacturer can advise on whether the clearance needs adjustment or whether their process can accommodate it.
Omini's engineering team regularly reviews DRC reports with customers during the RFQ process. Sharing your trend data early allows the team to flag potential issues before tooling is cut, saving time and money on both sides.
Involve your manufacturer when you encounter:
- New package types you have not used before, such as a fine-pitch BGA or a QFN with an exposed pad.
- High layer count boards where copper balance and warpage are concerns.
- Mixed-technology assemblies with through-hole and SMT components.
- Repeated DRC errors that you cannot resolve internally.
For related risk assessment approaches, see How to Evaluate SMT Assembly Risk from FOPLP and Thermal Processing Trends and How to Evaluate SMT Assembly Risk from PCB Design and KiCad Trends. For broader context on how industry dynamics affect assembly decisions, review How to Evaluate SMT Assembly Risk from Acquisition and CEO Trends and How to Evaluate SMT Assembly Risk from Aerospace and Industrial Automation Trends. Manufacturing-side considerations are covered in How to Evaluate SMT Assembly Risk from PCB Design and PCB Manufacturing Trends.
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FAQ
Why does KiCad DRC matter for SMT assembly risk?
KiCad DRC checks your layout against design rules that directly affect SMT assembly. Clearance violations can cause solder bridges, missing solder mask can cause shorts, and footprint errors can lead to tombstoning or poor wetting. Catching these before fabrication reduces assembly risk and rework.
What are common mistakes engineers make when using KiCad DRC for SMT?
A common mistake is treating all DRC errors as equal. A clearance violation between two BGA pads is high risk, while a silkscreen overlap is cosmetic. Another mistake is ignoring courtyard violations, which can cause pick-and-place collisions. Engineers also forget to run DRC after final component changes, leaving stale results.
How do I verify SMT assembly risk before sending files to a manufacturer?
Run a final DRC with your assembly-specific rules, then review each error class. Check footprint land patterns against IPC-7351, verify BGA fanout and via-in-pad, and confirm solder mask openings match pad sizes. Export a DRC report and share it with your EMS provider to align on risk.
What information should I include in an RFQ to help the manufacturer assess SMT risk?
Include your KiCad DRC report, the design rules used, and any known exceptions. Provide the BOM with manufacturer part numbers, the centroid file, and the stackup. Mention moisture-sensitive components and any special reflow requirements. This helps the manufacturer plan stencil design, inspection, and test strategy.
How do DRC trends help predict SMT assembly yield?
If DRC error counts decrease across revisions, the design is maturing. If new errors appear after a change, you can trace them to a specific edit. Trends also show recurring issues like insufficient clearances near connectors, which often cause assembly defects. Tracking these trends helps you prioritize fixes.
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