Direct Answer
Choose ENIG for fine-pitch SMT, BGA coplanarity, storage margin, and exposed-pad flatness. Choose HASL only when pad topography and shorter handling windows are acceptable.
Engineering Context
ENIG and HASL are not interchangeable labels on a quote form. They change the process risk, the inspection conversation, and the assumptions the assembler has to accept before release.
The first-principles question is not which option is more popular. The question is which option removes the limiting risk in this board: pad condition, storage window, component pitch, inspection access, material behavior, process capability, or drawing control.
Keep the decision bounded to the released design package. If the drawing, BOM, fabrication notes, or assembler requirements do not state the controlling assumption, the quote should treat the choice as unresolved rather than silently substitutable.
Decision Criteria
- engineering fit
- risk trigger
- RFQ handoff
Comparison Table
| Criterion | ENIG | HASL | Decision note |
|---|---|---|---|
| Best fit | fine-pitch SMT, BGA coplanarity, or longer bare-board storage controls the finish choice. | the board is simple and the assembler accepts solder-coated pad topography. | Choose the option that removes a real build risk. |
| Main limitation | higher finish cost and plating process control. | weaker fit for flat pads, dense SMT, or long storage unless solderability, alloy, and assembler acceptance are explicit. | Neither side is universally better. |
| RFQ input | name ENIG in fabrication notes. | confirm HASL is allowed by the drawing and assembler. | Make the selected assumption explicit. |
Decision Tree
1. If the decision is controlled by engineering fit, compare the smallest component, fastest signal, or most restrictive inspection requirement first. 2. If ENIG removes that risk, specify it directly in the drawing or RFQ. 3. If HASL meets the same electrical, assembly, inspection, and schedule constraints with less complexity, keep the simpler option. 4. If the answer depends on missing stackup, BOM, finish, or inspection data, keep the page as a decision guide and close the RFQ inputs before release.
What Changes The Decision
Use ENIG when the board risk is controlled by the conditions listed in the ENIG column and the added control is justified by assembly yield, electrical behavior, inspection, reliability, or storage margin.
Use HASL only when the HASL column remains true after checking component geometry, process assumptions, drawing notes, and assembler acceptance.
Do not use this comparison to invent numeric tolerances, thicknesses, shelf-life promises, alloy composition, compliance statements, or supplier capability claims. Those belong in the released specification, applicable standard, or supplier capability review.
Recommended Use Cases
- Use ENIG for BGA, QFN, fine-pitch SMT, or longer bare-board storage.
- Use HASL for simple boards with tolerant component geometry when the assembler accepts the finish.
Limitations
- ENIG: higher finish cost and plating process control.
- HASL: weaker fit for flat pads, dense SMT, or long storage unless solderability, alloy, and assembler acceptance are explicit.
RFQ Handoff
Before RFQ, state the selected option, allowed alternates, inspection expectations, and any component packages or performance constraints that make one side unacceptable.
If HASL is allowed, confirm that the assembler accepts the actual package mix and process condition. If ENIG is required, state it directly instead of relying on a generic default.
A quote that does not normalize these assumptions is not a comparable quote; it is a different manufacturing condition.
Source Notes
- ENIG finish specification boundary - IPC-4552 ENIG plating standard (standard).
Source fact: IPC-4552 is the source boundary for electroless nickel immersion gold surface-finish specification context. Omini interpretation: Use this to frame ENIG as a controlled fabrication finish that must be named in drawings and verified by the fabricator. Allowed usage: Use on ENIG entity, finish comparison, and surface-finish decision pages.
- Printed-board solderability source boundary - IPC J-STD-003 solderability tests for printed boards (standard).
Source fact: IPC J-STD-003 is the source boundary for solderability test context on printed boards. Omini interpretation: Use this to keep HASL discussion tied to solderability verification and board-level acceptance review, not unsupported assumptions about universal assembly suitability. Allowed usage: Use on HASL, surface-finish comparison, RFQ readiness, and assembly-risk pages when solderability is part of the decision.
- Solder alloy assumption boundary - IPC J-STD-006 electronic grade solder alloys (standard).
Source fact: IPC J-STD-006 is the source boundary for electronic-grade solder alloy context. Omini interpretation: Use this to require explicit solder-alloy assumptions when a solder-coated finish such as HASL affects drawing notes, RoHS expectations, assembly review, or alternate finish approval. Allowed usage: Use on HASL, solderability, surface-finish comparison, and RFQ handoff pages.
- IPC standards source boundary - IPC official resources (standard).
Source fact: IPC official resources are used to locate standards context and public summaries, while paid standard text remains outside the repository. Omini interpretation: Use this to separate standards-backed engineering framing from copied acceptance criteria or unsupported numeric claims. Allowed usage: Use when a page needs IPC context but does not have a narrower public source registered yet.
- Existing OminiPCB repository content (internal): May seed structure and internal links; engineering claims still need external verification when specifications are involved.
This page stores original engineering guidance only. It does not reproduce paid standard text, datasheet tables, competitor claims, prices, or certification claims.
CTA
Request a PCB quote when the selected material, finish, stackup, inspection scope, quantity, and lead time are ready for engineering review.