Direkte Antwort
Evaluate PCB manufacturing risk by comparing your EasyEDA design decisions—stackup, trace width, spacing, drill size, annular ring, and surface finish—against your fabricator's stated minimum capabilities before exporting Gerbers. A design that passes EasyEDA's internal DRC can still fail on the fab floor because the tool checks your rules, not the manufacturer's. Run a separate DFM analysis on the exported Gerber files, and include stackup, material, finish, and test requirements in your RFQ to close the gap between design intent and fabrication reality.
Why PCB Design Decisions Drive Manufacturing Risk
Manufacturing risk is not introduced when the fab receives your files; it is introduced when you choose trace widths, via sizes, layer stackup, and materials in the schematic and layout editor. The fab floor executes what the design files specify. If those specifications violate process limits, the board either fails during fabrication or passes with latent reliability issues that surface during assembly or field use.
The most common risk categories trace directly to design choices:
- Copper weight and trace width: A 1 oz copper layer with a 6 mil trace may be fine for a standard board, but if your fab's minimum is 8 mil for that copper weight, you will get yield loss or open circuits.
- Drill size and aspect ratio: A 0.2 mm drill on a 2.0 mm thick board creates a 10:1 aspect ratio. Many fabs cap at 8:1 for standard through-hole plating. The hole may not plate uniformly, causing barrel cracks.
- Spacing between nets: Clearance violations cause shorts, especially on inner layers where visual inspection is impossible.
- Annular ring: A via with insufficient copper surrounding the drilled hole risks breakout, which can sever the connection between layers.
EasyEDA gives you full control over these variables. The risk is not the tool; it is how you use it. The design rules check (DRC) in EasyEDA validates against rules you define, not against the fab's process window. If you set your own minimums to match the fab's published capabilities, the DRC becomes a useful gate. If you leave defaults or set aggressive values, the DRC gives false confidence.
Evaluating Stackup and Material Choices in EasyEDA
The stackup is the single highest-leverage decision for manufacturing risk. It determines layer count, board thickness, copper weight, impedance control, and material cost. In EasyEDA, the layer stack manager lets you define the number of layers, copper weights, and dielectric thickness. Each of these choices must be validated against what your fab can actually produce.
Start with the fab's standard stackup, not a custom one. Standard stackups use prepreg and core combinations that the fab has already qualified. Custom stackups require engineering review, longer lead times, and higher risk of impedance variation. If your design needs controlled impedance, specify the target impedance and the layer pair, and let the fab recommend the dielectric thickness and spacing.
Material selection is equally important. FR-4 is the default for most prototypes, but the grade matters. Standard FR-4 has a glass transition temperature (Tg) around 130–140°C. If your board goes through lead-free reflow at 245–260°C peak, a low-Tg laminate can experience warpage or delamination. For boards with multiple reflow cycles or high operating temperatures, specify a mid-Tg or high-Tg laminate (170°C or higher). The material choice affects both cost and reliability, so match it to the assembly process and end-use environment.
For high-frequency designs, standard FR-4 has a dissipation factor that increases with frequency, causing signal loss. PTFE-based laminates or hydrocarbon ceramics are better choices, but they introduce different manufacturing constraints such as moisture sensitivity and specialized drilling. If you are evaluating materials for RF or high-speed applications, review the material risk factors separately. See How to Evaluate PCB Materials Risk from PCB Manufacturing and PTFE Trends for a deeper look at laminate selection trade-offs.
> Practical note: When you define a custom stackup in EasyEDA, export the stackup table and include it in your RFQ. A fab cannot quote accurately or build reliably if it has to guess your dielectric thickness or copper weight.
Running a DFM Check on Gerber Files, Not Just the Schematic
EasyEDA's DRC checks the schematic and layout for electrical connectivity errors, short circuits, and missing connections. It does not check for manufacturing-specific issues such as minimum annular ring, solder mask sliver, copper-to-edge clearance, or drill-to-copper spacing. These are geometric constraints that only become visible in the Gerber files.
After you export Gerbers and drill files from EasyEDA, run a dedicated DFM analysis. A DFM tool evaluates the actual copper, solder mask, and drill data against the fab's process capabilities. The key parameters to verify are:
- Minimum trace width and spacing on each copper layer
- Minimum annular ring for vias and through-holes
- Drill size against the fab's minimum and maximum limits
- Copper-to-edge clearance for routed board outlines
- Solder mask expansion around pads and vias
- Silkscreen-to-pad clearance to prevent solderability issues
- Thermal relief on planes connected to through-holes
A common mistake is running the DFM check on the EasyEDA project file instead of the exported Gerbers. The project file contains design intent; the Gerbers contain the actual manufacturing data. If your export settings are wrong—for example, if you exclude a copper layer or use the wrong drill file format—the DFM check will not catch it because it is checking the wrong data.
Another mistake is ignoring the fab's specific capabilities and relying on generic DFM rules. Different fabs have different minimums. A board that passes a generic DFM check may still fail at a fab with tighter process windows. Always download the fab's capability sheet and compare your design against those specific numbers.
Surface Finish Selection and Its Impact on Assembly Risk
Surface finish is a design decision that directly affects solderability, shelf life, and assembly yield. In EasyEDA, you select the surface finish when you generate the fabrication files or place the order. The choice should be driven by your component package types and assembly process, not by habit.
HASL (hot air solder leveling) is the most cost-effective finish. It has excellent solderability and is fine for through-hole components and larger SMD packages. However, HASL leaves an uneven surface due to the solder coating thickness variation. Fine-pitch components such as 0.4 mm pitch QFPs or BGAs can experience solder bridging or poor coplanarity on HASL finishes. If your design uses fine-pitch packages, HASL is a risk.
ENIG (electroless nickel immersion gold) provides a flat surface, good corrosion resistance, and long shelf life. It is the standard choice for BGAs, fine-pitch components, and boards with exposed gold contacts such as edge connectors. The trade-off is cost and a potential reliability issue called "black pad" if the immersion gold process is not well controlled. For cost-sensitive prototypes where fine-pitch assembly is not required, ENIG may be overkill.
OSP (organic solderability preservative) is a low-cost finish that provides good solderability for boards assembled shortly after fabrication. It has a limited shelf life, typically 6–12 months, and is sensitive to handling. OSP is a reasonable choice for prototypes with standard SMD components and immediate assembly.
The surface finish also affects test points. If you rely on flying probe or bed-of-nails testing, the finish must provide a reliable contact surface. ENIG is the best choice for testability; OSP can be problematic if the board sits too long before testing.
For boards that go through multiple reflow cycles or operate in harsh environments, the finish choice becomes a reliability decision. Match the finish to the assembly process and the end-use conditions. If you are evaluating assembly risk from a broader perspective, including component sourcing and process constraints, review How to Evaluate SMT Assembly Risk from PCB Manufacturing and Sourcing Trends for additional context.
Using IPC Standards as Design and Qualification References
IPC standards provide a framework for design and qualification, but they are not a substitute for your fab's specific capabilities. IPC-2221 and IPC-2222 define the general design guidelines for PCB layout, including conductor spacing, minimum annular ring, and hole sizes. IPC-6012 covers the qualification and performance requirements for rigid PCBs, including copper plating thickness, solderability, and visual inspection criteria.
These standards are useful because they give you a baseline for what is generally manufacturable. For example, IPC-2221 provides guidance on conductor spacing based on voltage and environmental conditions. IPC-6012 defines the minimum plating thickness in the hole barrel and the acceptable level of annular ring breakout.
However, IPC standards are minimums, not targets. A design that meets IPC-2221 may still be difficult for a specific fab to build if that fab has tighter process controls or different equipment. Conversely, a fab may have capabilities that exceed the IPC minimums, allowing you to design with smaller features than the standard suggests.
When you use IPC standards in your design review, treat them as a starting point. The final authority is the fab's capability sheet and the DFM analysis results. If you are designing to a specific performance class (Class 2 or Class 3), the requirements are stricter. Class 3 boards, used in high-reliability applications, require tighter tolerances and more rigorous inspection. If your design targets Class 3, you should state that in the RFQ so the fab can adjust its process controls and inspection criteria.
For material specifications, IPC-4101 defines the requirements for base materials such as FR-4 and other laminates. If you need a specific material grade, reference the IPC-4101 slash sheet in your RFQ. For material or process testing, IPC-TM-650 describes the test methods used to verify properties such as peel strength, solderability, and thermal stress resistance.
> Caution: Do not assume that meeting IPC-6012 Class 2 automatically means your board will pass your fab's incoming inspection. The fab may have additional customer-specific requirements or internal standards that are stricter than the IPC baseline.
Common Mistakes in EasyEDA That Increase Manufacturing Risk
Several recurring mistakes appear when engineers design PCBs in EasyEDA and send them to fabrication. Recognizing these patterns helps you avoid them in your own designs.
Ignoring the fab's design rules: EasyEDA has a design rules editor where you can set minimum trace width, spacing, and drill size. Many engineers leave the defaults or set values based on a previous fab. Each fab has different capabilities. Before you start layout, download the target fab's capability sheet and enter those values into EasyEDA's design rules.
Using non-standard drill sizes: EasyEDA's via and hole library includes metric and imperial sizes. Some engineers choose a drill size that is not available in the fab's standard tooling. Non-standard drills require special tooling or are not offered at all. Stick to the fab's standard drill sizes, which are usually listed in the capability sheet.
Forgetting solder mask expansion: Solder mask expansion is the amount of mask that is pulled back from the pad edge. If the expansion is too small, the mask overlaps the pad and reduces the solderable area. If it is too large, the pad is exposed and can cause solder bridging. EasyEDA has a default expansion, but it may not match the fab's recommendation.
Not checking impedance requirements: If your design has controlled impedance traces, you must specify the impedance value and the layer pair. The fab calculates the trace width and spacing based on the stackup and dielectric constant. If you do not specify impedance, the fab will use its standard stackup, and your traces may not meet the required impedance.
Skipping the DFM check on Gerbers: As discussed earlier, the DRC in EasyEDA is not a DFM check. Export the Gerbers and run a separate DFM analysis. This is the single most effective step to reduce manufacturing risk.
Missing thermal relief on plane connections: When a through-hole connects to a copper pour, the thermal relief determines how much copper connects the hole to the plane. Without thermal relief, the hole acts as a heat sink during soldering, causing poor solder joints. EasyEDA allows you to set thermal relief on vias and through-holes, but the default may not be enabled.
What to Include in the RFQ to Reduce Fabrication Surprises
The RFQ is the last opportunity to align your design intent with the fab's process capabilities. A complete RFQ eliminates ambiguity and prevents the fab from making assumptions that lead to rework or failure.
Include the following information in every RFQ:
- Layer count and board thickness: Specify the exact number of layers and the final board thickness, including copper and solder mask.
- Copper weight: Specify the copper weight for each layer. Inner layers and outer layers can have different copper weights if needed.
- Surface finish: State the finish explicitly, such as HASL lead-free, ENIG, or OSP. Do not leave it to the fab's default.
- Solder mask color and type: Specify the color and whether you need a matte or gloss finish. This affects inspection and aesthetics.
- Impedance requirements: If applicable, list the impedance values, the layer pairs, and the tolerance.
- Minimum trace width and spacing: State the minimums for your design so the fab can verify against its capabilities.
- Drill sizes and tolerances: List the drill sizes and any special tolerances for plated or non-plated holes.
- Test requirements: Specify whether you need flying probe testing, bed-of-nails testing, or impedance testing. This affects the fab's process and your cost.
- Operating environment: Describe the end-use environment, such as high temperature, high humidity, or vibration. The fab can recommend appropriate materials and finishes.
A common mistake is sending a vague RFQ with only the Gerber files and expecting the fab to figure out the details. The fab will make assumptions, and those assumptions may not match your intent. For example, if you do not specify the surface finish, the fab may default to HASL, which is unsuitable for fine-pitch BGAs.
If your design has special requirements, such as edge plating, castellated holes, or controlled impedance, state them explicitly in the RFQ. These features require additional process steps and may not be included in the standard quote.
For assembly-related risk, the RFQ should also include the BOM status, component package types, and any special assembly requirements. If you are evaluating assembly risk from a thermal or process perspective, review How to Evaluate SMT Assembly Risk from FOPLP and Thermal Processing Trends for guidance on thermal profile and package-level considerations.
A Practical Example: Evaluating a 4-Layer Board in EasyEDA
Consider a 4-layer board with a standard FR-4 stackup: 1.6 mm total thickness, 1 oz copper on all layers, and a green solder mask. The design uses 0.3 mm vias, 8 mil traces, and a 0.5 mm pitch QFP on the top layer.
Before generating Gerbers, you check the fab's capability sheet. The fab lists a minimum trace width of 6 mil, a minimum drill size of 0.2 mm, and a minimum annular ring of 4 mil. Your design meets these minimums. You also check the aspect ratio: 0.3 mm drill on a 1.6 mm board is a 5.3:1 ratio, which is within the fab's 8:1 limit.
You run EasyEDA's DRC and it passes. You export the Gerbers and drill files, then run a DFM check. The DFM tool flags a solder mask sliver between two adjacent QFP pads. The mask expansion is too small, leaving a narrow web of mask that may peel during fabrication. You adjust the mask expansion in EasyEDA and re-export.
You also notice that the DFM tool flags a via with an annular ring of only 3 mil, below the fab's 4 mil minimum. You increase the via pad size in EasyEDA and re-run the DFM check. The design now passes.
In the RFQ, you specify the 4-layer stackup, 1 oz copper, ENIG finish, and flying probe testing. You also note that the QFP is 0.5 mm pitch, so the fab knows to expect fine-pitch assembly. The fab confirms the design is manufacturable and provides a quote.
This example illustrates the workflow: design in EasyEDA, check against the fab's capabilities, export Gerbers, run DFM, fix issues, and communicate clearly in the RFQ. Skipping any of these steps increases the risk of fabrication failure or assembly defects.
For a broader view of how design decisions affect assembly yield, including component placement and solder paste considerations, see How to Evaluate SMT Assembly Risk from PCB Manufacturing and Renewable Energy Trends. For high-speed or advanced technology considerations, such as impedance control and signal integrity, review How to Evaluate Advanced PCB Technology Risk from High-Speed PCB and Integrity Trends.
FAQ
Why does PCB design affect manufacturing risk?
Design choices like trace width, spacing, via size, and stackup directly determine whether a board can be fabricated reliably. If your design violates a fab's minimum capabilities, you risk open circuits, shorts, or delamination during production.
Where do engineers make mistakes when using EasyEDA for PCB manufacturing?
Common mistakes include ignoring the fab's design rules, using non-standard drill sizes, forgetting to add solder mask expansion, and not checking impedance requirements. EasyEDA has a DRC tool, but it only checks against your own rules, not the fab's capabilities.
How can I verify PCB manufacturability before sending files to a fab?
Export Gerber files and drill files, then run a DFM analysis using a tool like Omini's DFM check or a standalone Gerber viewer. Verify that your trace widths, spacing, annular rings, and hole sizes meet the fab's stated minimums.
What information should I include in the RFQ to reduce PCB manufacturing risk?
Include the layer count, board thickness, copper weight, surface finish, solder mask color, impedance requirements, and any special tolerances. Also specify the intended operating environment, such as high temperature or high humidity, so the fab can recommend appropriate materials.
How does EasyEDA's design rules check (DRC) help with PCB manufacturing risk?
EasyEDA's DRC checks for basic design errors like short circuits and missing connections, but it does not check for manufacturing-specific issues like minimum annular ring or solder mask sliver. You must still compare your design against the fab's capabilities.
What is the role of surface finish in PCB manufacturing risk?
Surface finish affects solderability, shelf life, and reliability. HASL is cost-effective but can have uneven surfaces for fine-pitch components. ENIG provides a flat surface and good corrosion resistance but is more expensive. Choose based on your assembly process and reliability needs.
> Engineering handoff note: How to Choose the Right Manufacturer for Flex PCB Fabrication before the release package is frozen.