Direct Answer
Choose the standard 1-2-1-2-1 6-layer stack-up—Signal, Ground, Signal, Power, Signal, Ground—for most digital designs, as it provides two solid reference planes and controlled impedance at the lowest manufacturing cost. Deviate only when mixed-signal isolation, very high-speed serial links, or heavy power distribution demands a different plane arrangement. Verify dielectric thickness, copper weight, and impedance targets with your manufacturer before releasing files.
The Default 6-Layer Stack-Up and Its Boundary Conditions
The most common 6-layer stack-up used across the PCB industry is the 1-2-1-2-1 arrangement:
| Layer | Function | Typical Copper Weight |
|---|---|---|
| L1 (Top) | Signal | 0.5 oz or 1 oz |
| L2 | Ground | 1 oz |
| L3 | Signal | 0.5 oz or 1 oz |
| L4 | Power | 1 oz |
| L5 | Signal | 0.5 oz or 1 oz |
| L6 (Bottom) | Ground | 0.5 oz or 1 oz |
This configuration places ground on L2 and L6, giving every signal layer an adjacent reference plane. L3 references L2 for impedance control, while L5 references L6. The power plane on L4 is sandwiched between two signal layers, which creates a natural inter-plane capacitance with L3 and L5 that helps with high-frequency decoupling.
The boundary conditions for this default stack-up are straightforward. It works well when your design has moderate signal speeds (up to approximately 10 Gbps on outer layers with proper routing), standard digital logic, and power requirements that can be satisfied with a single power plane. It also assumes you are using through-hole vias only, which keeps lamination cycles at two and drilling at one pass.
If your design fits these parameters, there is no engineering reason to change the stack-up. The default arrangement is cost-effective, manufacturable, and well-understood by fabrication shops. Changing it adds cost and lead time without improving performance.
The Engineering Principle Behind Stack-Up Selection
Signal Integrity: Reference Planes and Return Current
The core principle governing stack-up selection is return current management. Every high-speed signal trace needs a continuous, adjacent reference plane to carry its return current. When a signal transitions between layers, the return current must also transition—typically through a via adjacent to the signal via.
In the default 1-2-1-2-1 stack-up, L1 and L3 reference L2 (ground), while L5 references L6 (ground). This means every signal layer has a solid ground reference directly beneath it. The distance between the signal layer and its reference plane determines the impedance of the trace. For a 50-ohm single-ended trace on L1 with a 4-mil dielectric to L2, you typically need a trace width around 7-8 mils with standard FR4 (dielectric constant approximately 4.2-4.5).
For differential pairs, the spacing between the two traces and the distance to the reference plane both affect impedance. A 100-ohm differential pair on L1 with a 4-mil dielectric typically requires 5-6 mil trace widths with 7-8 mil spacing. These values vary with the exact dielectric constant and thickness, which is why you must confirm your manufacturer's stack-up data.
Power Integrity: Plane Capacitance and Decoupling
The default stack-up places power on L4, with L3 and L5 adjacent. This creates two distributed capacitors: one between L3 and L4, and one between L4 and L5. The capacitance value depends on the dielectric thickness and the dielectric constant. With a 4-mil FR4 dielectric, the inter-plane capacitance is approximately 200-250 pF per square inch.
This distributed capacitance helps suppress power supply noise at high frequencies, where discrete decoupling capacitors become inductive and lose effectiveness. For most digital designs, this is sufficient. If your design has very high transient current demands—such as FPGAs with hundreds of simultaneously switching outputs—you may need to reduce the dielectric thickness between power and ground to increase capacitance, or add a dedicated power-ground plane pair.
Crosstalk and Isolation
Adjacent signal layers in a 6-layer board can couple to each other through the dielectric. In the default stack-up, L3 and L5 are separated by the power plane on L4. This provides natural isolation. However, if you route high-speed signals on both L3 and L5, you should route them perpendicular to each other to minimize broadside coupling.
For analog and digital separation, the default stack-up does not inherently isolate sensitive analog signals. You must rely on physical separation, guard traces, and proper grounding strategies. If your design has a sensitive analog section that cannot tolerate digital switching noise, consider whether the default stack-up is sufficient or whether you need a modified arrangement.
When to Deviate from the Default Stack-Up
Mixed-Signal Designs Requiring Isolation
If your board contains both sensitive analog circuits and high-speed digital logic, the default stack-up may not provide adequate isolation. The power plane on L4 is shared across the entire board, which means digital switching noise on the power plane can couple into analog circuits.
One common modification is to split the power plane into separate analog and digital sections. This requires careful planning of the split location and ensuring that no signal traces cross the split. An alternative is to use a dedicated ground plane adjacent to the analog signal layer, which means changing the layer order to place ground on both L2 and L4, with power on L3 or L5.
Another option is to use a 1-1-2-2-1-1 arrangement where L2 and L3 are both ground planes, providing a shielded environment for critical signals routed between them. This is more expensive due to the additional copper weight and thinner dielectrics, but it offers superior isolation.
Very High-Speed Serial Links
For designs with 25 Gbps or faster serial links, the default stack-up may not provide sufficient signal integrity. High-speed links require tight impedance control, which means precise dielectric thickness and trace width control. They also benefit from thinner dielectrics between the signal layer and its reference plane, which reduces the trace width needed for a given impedance and reduces radiation.
A common modification for high-speed designs is to use a stack-up where the outer signal layers have thinner dielectrics to the ground planes beneath them. For example, a 3-mil dielectric on L1-L2 and L5-L6, with a thicker core between L2 and L3. This reduces the trace width for 50-ohm impedance to approximately 5-6 mils, which is easier to route in dense designs.
You should also consider the laminate material. Standard FR4 has a dielectric constant that varies with frequency and temperature, which can cause impedance drift. For very high-speed designs, consider low-loss laminates such as Rogers or Isola materials. The choice between FR4 and Rogers materials depends on your frequency, loss budget, and cost constraints—see our guide on FR4 vs Rogers PCB Material: Which One Should I Choose for My Products? for a detailed comparison.
Heavy Power Distribution Requirements
If your design draws high current—such as power amplifiers, motor drivers, or high-power LED arrays—the default stack-up with a single power plane may not have sufficient copper cross-section for the current path. A 1 oz copper plane is approximately 1.4 mils thick and can carry roughly 1 amp per 10 mils of width for a 10°C temperature rise, depending on the ambient temperature and cooling.
For high-current designs, you may need to increase the copper weight on the power plane to 2 oz or even 3 oz. This increases the cost of the board but is necessary to prevent excessive voltage drop and heating. Alternatively, you can use multiple power planes on different layers, but this requires changing the layer order and may reduce the number of available signal layers.
Manufacturing Constraints and DFM Considerations
Via Types and Their Cost Impact
The default 6-layer stack-up uses through-hole vias exclusively. This is the most cost-effective approach because it requires only one drilling pass and one plating cycle. Through-hole vias in a 6-layer board typically have a minimum drill size of 0.2 mm (8 mils) and a finished hole size of 0.15 mm (6 mils), depending on the manufacturer's capability.
Blind and buried vias increase the layer count of the lamination process. A buried via between L2 and L5 requires an additional lamination cycle before the outer layers are added. Blind vias from L1 to L2 or L5 to L6 require laser drilling and sequential lamination. Each additional via type adds cost and lead time.
Before specifying blind or buried vias, ask yourself whether the design truly requires them. In many cases, a through-hole via with a small drill size can achieve the same routing density at lower cost. If you must use blind or buried vias, discuss the capability and cost with your manufacturer early in the design process. The common DFM issues and how to avoid them in PCB design article covers via-related pitfalls in more detail.
Dielectric Thickness and Impedance Control
The dielectric thickness between a signal layer and its reference plane determines the trace width needed for a target impedance. Standard FR4 prepreg and core materials come in specific thicknesses, typically 3 mil, 4 mil, 5 mil, and 6 mil. The manufacturer's stack-up will use a combination of these materials to achieve the total board thickness.
For impedance-controlled traces, you must specify the target impedance and the layer on which each net is routed. The manufacturer will then adjust the trace width to achieve the target impedance based on their actual dielectric thickness and material properties. This is why you should not assume that a trace width that worked on a previous board will work on a new one—the dielectric thickness may differ.
IPC-4101 defines the specification for laminate materials used in rigid PCBs, including FR4 and high-frequency materials. When discussing your stack-up with a manufacturer, reference the IPC-4101 material grade you expect, such as IPC-4101/21 for standard FR4 or IPC-4101/99 for low-loss materials.
Copper Weight and Etching Tolerance
Copper weight affects both the impedance and the manufacturability of your board. Standard copper weights are 0.5 oz (17.5 µm), 1 oz (35 µm), and 2 oz (70 µm). The copper weight on the outer layers is typically specified as the base copper weight before plating. Through-hole plating adds approximately 0.5-1 oz of copper to the outer layers and the via barrels.
For impedance-controlled traces, the copper thickness affects the trace impedance. Thicker copper reduces the impedance for a given trace width. The manufacturer's impedance calculator will account for the final copper thickness, including plating. If you specify 1 oz copper on the outer layers, the final copper thickness after plating may be 1.5-2 oz, which changes the impedance.
> Practical note: When you request impedance control, the manufacturer will adjust trace widths to hit the target impedance based on their actual stack-up. Do not fix trace widths in your design rules unless you have already confirmed them with your manufacturer. A 50-ohm trace on one manufacturer's stack-up may be 7 mils, while on another it may be 8 mils.
Board Thickness and Warpage
The total thickness of a 6-layer board depends on the dielectric materials and copper weights used. A typical 6-layer board is 1.6 mm (62 mils) thick, which is the industry standard. However, you can specify thinner or thicker boards depending on your mechanical constraints.
Thinner boards (1.0-1.2 mm) are lighter and fit in tighter enclosures, but they are more prone to warpage, especially with asymmetric copper distribution. Thicker boards (2.0-2.4 mm) are stiffer and provide better mechanical support, but they require longer drill times and may have higher aspect ratios for vias.
To minimize warpage, keep the copper distribution balanced across the layers. If L1 has heavy copper fills, ensure L6 has similar copper coverage. The same applies to L2 and L5, and L3 and L4. An unbalanced stack-up can cause the board to bow or twist after reflow soldering, which can lead to assembly defects. The SMT AOI inspection coverage article discusses how warpage and other defects are detected during assembly.
Common Mistakes That Create Rework During DFM Review
Mistake 1: Not Specifying Impedance Requirements
Many designers assume that the manufacturer will automatically control impedance on all traces. This is not the case. Impedance control requires explicit specification of the target impedance, the layer, and the net name for each controlled trace. If you do not specify this, the manufacturer will produce the board with standard trace widths, which may not meet your signal integrity requirements.
Mistake 2: Ignoring the Manufacturer's Stack-Up Capability
Each manufacturer has a set of standard stack-ups that they have already validated. If you design a custom stack-up that does not match their standard materials, the manufacturer may need to order special materials, which increases lead time and cost. Before designing a custom stack-up, ask your manufacturer for their standard 6-layer stack-up options.
Mistake 3: Routing Traces Over Plane Splits
If you split the power plane on L4 into multiple voltage domains, ensure that no signal traces on L3 or L5 cross the split. Crossing a plane split forces the return current to take a longer path, which increases loop area and can cause signal integrity problems. If you must cross a split, use a ground plane on the adjacent layer or add stitching capacitors across the split.
Mistake 4: Using Blind and Buried Vias Without Justification
Blind and buried vias are often specified out of habit or because a previous design used them. They add significant cost and lead time. Review your routing to determine if through-hole vias can achieve the same result. In many cases, a small through-hole via (0.2 mm drill) can be placed in the same location as a blind via.
Mistake 5: Not Requesting a Stack-Up Report
Always request a stack-up report from your manufacturer before releasing the design for production. This report shows the layer order, dielectric materials and thicknesses, copper weights, and impedance calculations. Review it carefully to ensure it matches your design requirements. If the manufacturer's stack-up differs from your assumptions, your impedance calculations may be wrong.
Review Checklist and Decision Table
Before sending your 6-layer PCB design to fabrication, use the following checklist to verify your stack-up:
| Check Item | What to Verify | Why It Matters |
|---|---|---|
| Layer order | Signal-Ground-Signal-Power-Signal-Ground | Provides reference planes for all signal layers |
| Dielectric thickness | Confirm with manufacturer's stack-up report | Determines trace width for target impedance |
| Copper weight | Confirm base and finished copper weight | Affects impedance, current capacity, and cost |
| Impedance requirements | Specify target impedance, layer, and net names | Ensures controlled impedance on critical traces |
| Via type | Through-hole only unless justified | Blind/buried vias increase cost and lead time |
| Plane splits | No signal traces crossing splits | Prevents return current discontinuity |
| Copper balance | Symmetric copper distribution across layers | Minimizes warpage during reflow |
| Material grade | IPC-4101 grade for laminate | Ensures consistent dielectric properties |
| Test coupons | Request impedance test coupons | Verifies impedance after fabrication |
Decision Table for Stack-Up Selection
| Design Condition | Recommended Stack-Up | Rationale |
|---|---|---|
| Digital logic, <10 Gbps, single power rail | Default 1-2-1-2-1 | Lowest cost, adequate SI/PI |
| Mixed analog/digital, sensitive analog section | Modified with split power plane or additional ground | Isolates noise sources |
| 25 Gbps+ serial links | Thin dielectrics on outer layers, low-loss laminate | Tight impedance control, reduced loss |
| High current, power distribution | Increased copper weight on power plane | Prevents voltage drop and heating |
| Dense routing, BGA with fine pitch | Consider blind vias on outer layers | Improves routing density, higher cost |
Questions to Ask Your Manufacturer
When you are ready to send your 6-layer design to fabrication, ask your manufacturer the following questions:
1. What is your standard 6-layer stack-up? Ask for the exact layer order, dielectric materials, and thicknesses. Compare this with your design assumptions.
2. What dielectric thickness tolerance do you hold? A ±10% tolerance on a 4-mil dielectric means the impedance can vary by approximately ±5%. This may be acceptable for some designs but not for others.
3. What copper weights do you offer for inner and outer layers? Confirm that your specified copper weight is available and understand the finished copper thickness after plating.
4. Can you control impedance to ±10% or better? Most manufacturers can achieve ±10% impedance tolerance, but some can achieve ±5% with tighter process control. This may affect cost.
5. Do you provide impedance test coupons? Test coupons are small test structures on the panel that are measured after fabrication to verify impedance. This is essential for high-speed designs.
6. What is your capability for blind and buried vias? If your design requires them, confirm the minimum drill size, aspect ratio, and additional cost.
7. What laminate materials do you stock? If you need low-loss materials, confirm availability and lead time. Standard FR4 is always available, but specialty materials may need to be ordered.
8. What is your standard board thickness tolerance? A 1.6 mm board typically has a tolerance of ±10%. If your mechanical enclosure requires tighter tolerance, discuss this with the manufacturer.
For a broader perspective on selecting a fabrication partner, review our guide on how to choose a reliable PCB manufacturer for your project. The same due diligence applies to verifying stack-up capability as to evaluating overall manufacturing quality.
Reliability and Qualification Considerations
IPC-6012 and Board Qualification
IPC-6012 is the qualification and performance specification for rigid PCBs. It defines the requirements for final board inspection, including conductor spacing, plating thickness, and solderability. When you receive your 6-layer boards, they should meet IPC-6012 Class 2 or Class 3 requirements, depending on your application. Class 3 is for high-reliability applications such as medical devices and aerospace systems.
The stack-up you choose affects your ability to meet IPC-6012 requirements. For example, if you use a very thin dielectric (2 mil) between a signal layer and its reference plane, the manufacturer must ensure that the dielectric withstands the voltage stress without breakdown. This is tested as part of the qualification process.
Material Testing and IPC-TM-650
IPC-TM-650 is the test methods manual used to evaluate laminate materials and finished boards. Tests include dielectric constant and dissipation factor measurement, peel strength, and thermal stress testing. If you are using a non-standard laminate, ask your manufacturer for test data from these methods to confirm the material meets your requirements.
For standard FR4, the dielectric constant is typically specified at 1 MHz and 1 GHz. The value at 1 GHz is more relevant for high-speed digital design. A typical FR4 has a dielectric constant of 4.2-4.5 at 1 GHz, with a dissipation factor of 0.015-0.020. Low-loss materials have dissipation factors below 0.005, which reduces signal attenuation at high frequencies.
Assembly Considerations
The stack-up also affects assembly yield. A board with excessive warpage can cause soldering defects, especially for large BGAs and QFNs. The flex PCB manufacturing process article discusses lamination and material selection principles that also apply to rigid boards, particularly regarding copper balance and thermal management.
During reflow soldering, the board expands and contracts with temperature. A balanced stack-up with symmetric copper distribution minimizes warpage. If your design has heavy copper on one side and light copper on the other, consider adding a copper pour on the opposite side to balance the thermal mass.
At Omini, we review stack-up designs as part of our DFM check before production. We verify that the layer order, dielectric materials, and copper weights are manufacturable and that impedance requirements are achievable. This review is part of our standard process for 6-layer and higher-layer-count boards.
Final Verification Before Release
Before you release your 6-layer design to fabrication, complete the following verification steps:
1. Confirm the layer order matches your design intent. A single layer swap can render the board non-functional.
2. Verify that all impedance-controlled nets are specified with target impedance, layer, and net name. Check that the trace widths in your layout match the manufacturer's recommended values.
3. Review the drill file to confirm that all vias are through-hole unless you have explicitly specified blind or buried vias. Check that the minimum drill size is within the manufacturer's capability.
4. Check for plane splits under high-speed traces. Use your CAD tool to visualize the reference plane beneath each critical trace.
5. Request a stack-up report from your manufacturer before production. Compare it with your design assumptions and flag any discrepancies.
6. Request impedance test coupons on the panel. These are low-cost additions that verify the impedance after fabrication and provide traceability for your quality records.
By following this process, you can select a 6-layer stack-up that meets your performance requirements without paying for unnecessary manufacturing complexity. The default 1-2-1-2-1 stack-up is the right choice for most designs, and deviations should be justified by specific engineering requirements.
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