Direct Answer
Select a symmetric multilayer stackup with 1.6 mm total thickness, 1 oz copper on outer layers, 0.5 oz on inner layers, and standard FR-4 (dielectric constant ~4.2) for most digital designs. Change this default only when controlled impedance, higher layer counts, high-current paths, or low-loss RF requirements demand different materials or dielectric spacing. Verify your stackup against the manufacturer's available core and prepreg combinations before releasing Gerbers to avoid costly DFM revisions.
The Default Stackup and Its Boundary Conditions
A 4-layer stackup with 1.6 mm total thickness remains the most practical starting point for the majority of digital PCB designs. The standard configuration places signal routing on the outer layers (top and bottom) and dedicates the two inner layers to power and ground planes. This arrangement gives you a solid return path for high-speed signals, reduces EMI, and keeps fabrication costs predictable.
The default copper weight matters. Outer layers at 1 oz (35 µm) handle standard component soldering and typical trace current requirements. Inner layers at 0.5 oz (17.5 µm) reduce material cost and are sufficient for power and ground planes in most designs. If your design carries more than 2 A through a trace, consider increasing copper weight on the relevant layer rather than widening the trace excessively.
The boundary conditions for this default stackup are straightforward. Total thickness of 1.6 mm matches standard connector and enclosure specifications. The dielectric constant of FR-4 at approximately 4.2 supports typical single-ended and differential impedance targets when the dielectric spacing is controlled. If your design requires impedance tolerance tighter than ±10%, or if your signal rise times are below 1 ns, you should evaluate whether the default stackup still meets your signal integrity requirements.
Core and Prepreg: How the Stackup Is Actually Built
A multilayer PCB is constructed by alternating rigid core material with prepreg (pre-impregnated glass fiber and resin) layers. The core is a fully cured laminate with copper foil already bonded to both sides. Prepreg is partially cured and acts as the adhesive layer that bonds cores together during lamination. Understanding this distinction is essential because it determines what dielectric thicknesses are actually achievable.
Core thickness is fixed by the laminate manufacturer. Prepreg thickness, however, varies depending on the resin content and the pressure applied during lamination. This means the final dielectric spacing between layers is not a continuous range of values but a discrete set determined by available core and prepreg combinations. When you specify a target impedance, your manufacturer will select the closest available combination that meets your requirement.
For a standard 4-layer 1.6 mm stackup, a typical construction uses a 1.1 mm core (with 0.5 oz copper on both sides) and two prepreg layers of approximately 0.2 mm each on the outer sides. The total thickness calculation must include copper weight, core thickness, prepreg thickness, and solder mask. If you specify a total thickness that does not match the available material combination, the manufacturer will either adjust the prepreg stack or flag the discrepancy during DFM review.
The dielectric spacing between the signal layer and its adjacent reference plane is the most critical dimension for impedance control. For a 50 Ω single-ended trace on an outer layer, a dielectric thickness of approximately 0.2 mm with 1 oz copper and standard FR-4 will yield a trace width near 0.35 mm. For inner-layer stripline traces, the spacing to both reference planes must be symmetric to maintain consistent impedance.
Material Selection: When FR-4 Is Not Enough
Standard FR-4 is suitable for digital designs with moderate signal speeds and benign environmental conditions. However, when your design moves into RF, high-speed serial links, or high-temperature environments, the material choice becomes a reliability decision rather than a cost decision. The three material properties that matter most are dielectric constant (Dk), dissipation factor or loss tangent (Df), and glass transition temperature (Tg).
For high-speed digital signals above 5 Gbps, standard FR-4's loss tangent of approximately 0.020 causes excessive signal attenuation over longer traces. Low-loss laminates such as Isola materials offer dissipation factors in the range of 0.005 to 0.010, significantly reducing insertion loss. If you are designing 10 Gbps Ethernet, PCIe Gen 4, or higher-speed serial links, specify a low-loss material from the start rather than discovering the limitation during signal integrity simulation. For a deeper comparison of laminate options, see Isola PCB Material: A Basic Introduction for Design and Manufacturing Decisions.
For RF designs, the dielectric constant tolerance and its stability across frequency become critical. Standard FR-4 has a Dk tolerance of roughly ±10%, which translates directly into impedance variation. RF laminates offer Dk tolerances of ±2% or better, enabling predictable impedance and consistent filter or antenna performance. The choice of RF material also affects copper roughness, which contributes to conductor loss at high frequencies. Smoother copper foils reduce loss but may increase material cost. Review the specific tradeoffs in How Do You Select RF PCB Material and the Most Commonly Used Types?.
High-temperature applications, such as automotive engine compartments or industrial controls, require materials with higher Tg. Standard FR-4 has a Tg around 130–140°C. Mid-Tg materials (150–170°C) and high-Tg materials (170–180°C) improve dimensional stability during reflow and reduce the risk of barrel cracking in plated vias under thermal cycling. If your assembly process uses lead-free solder with peak reflow temperatures near 245–260°C, a higher Tg material provides additional margin against delamination.
> Practical note: When you change from FR-4 to a low-loss or RF laminate, the dielectric constant changes, which changes the required trace width for a given impedance. Recalculate your impedance targets with the new material's Dk value rather than assuming the same trace geometry will work.
Copper Weight, Plane Integrity, and Current Handling
Copper weight selection affects more than just trace current capacity. It influences impedance, etch tolerance, minimum trace width, and the reliability of plated through-holes. Standard 1 oz copper supports a minimum trace width of approximately 0.1 mm with standard etching processes. If you need finer traces, consider 0.5 oz copper on signal layers, which allows narrower traces for the same impedance target.
For power distribution, the plane copper weight determines the DC resistance of the power and ground network. A 0.5 oz plane has approximately twice the sheet resistance of a 1 oz plane. If your design has high-current sections, such as a motor driver or a power supply stage, increase the copper weight on those specific layers to 2 oz or more. This is more reliable than relying on multiple vias to carry current between layers.
Copper balance across the board cross-section is a DFM requirement that affects fabrication yield. If one side of the board has significantly more copper than the other, the board can warp during lamination and reflow. IPC-2221 and IPC-2222 provide the general design framework for PCB layout, including guidance on conductor spacing and board dimensions. For fabrication reliability, IPC-6012 defines the qualification and performance scope for rigid PCBs, covering aspects such as copper adhesion and thermal stress resistance.
The drill aspect ratio is another constraint tied to copper weight and board thickness. The aspect ratio is the ratio of board thickness to the smallest drilled hole diameter. Most manufacturers can reliably drill aspect ratios up to 10:1 for standard through-holes. A 1.6 mm board with a 0.2 mm via therefore has an aspect ratio of 8:1, which is within standard capability. If you need smaller vias or a thicker board, verify the aspect ratio against your manufacturer's capabilities before finalizing the stackup.
Impedance Control and Reference Plane Strategy
Controlled impedance is required when signal integrity analysis shows that reflections or crosstalk would otherwise degrade the signal. The decision to specify controlled impedance should be driven by the signal rise time and trace length, not by a general preference. For traces shorter than one-tenth of the signal wavelength, impedance control is usually unnecessary.
When you do specify controlled impedance, the reference plane directly beneath the signal trace must be continuous. A gap in the reference plane, such as a split between different ground regions, disrupts the return current path and causes impedance discontinuity. This is a common source of EMI and signal integrity problems that are difficult to debug after fabrication.
For high-speed signals, placing them on outer layers with a solid reference plane directly beneath minimizes via transitions. Every via transition introduces a parasitic inductance and capacitance that degrades signal quality. If your design requires layer changes for high-speed signals, pair the via with a ground via adjacent to it to provide a low-inductance return path.
The impedance tolerance you specify affects fabrication cost. A tolerance of ±10% is achievable with standard FR-4 and standard manufacturing processes. Tighter tolerances of ±5% require more precise dielectric thickness control, which may require selecting a different prepreg combination or a laminate with tighter Dk tolerance. Specify the impedance target and tolerance in the fabrication notes for each controlled-impedance net, and verify that the manufacturer's test coupon includes the same stackup as your board.
Common Stackup Mistakes That Cause DFM Rework
Several recurring mistakes in stackup specification create rework during DFM review. The most common is specifying a total board thickness that does not match any available core and prepreg combination. This forces the manufacturer to either adjust the stackup or reject the design for revision. Always verify your total thickness against the manufacturer's standard stackup options before releasing Gerbers.
Another frequent error is asymmetric stackups. An asymmetric layer arrangement, such as placing all signal layers on one side of the board, causes differential thermal expansion during lamination and reflow. This leads to board warpage, which affects assembly yield, particularly for surface-mount components with fine pitch. IPC-6012 covers the performance requirements for rigid PCBs, including warpage limits, but the design rule is simple: keep the stackup symmetric about the center line.
A third mistake is ignoring the minimum dielectric spacing for the chosen material. If you specify a dielectric thickness that is too thin for the prepreg available, the manufacturer cannot achieve the required impedance or voltage isolation. This is especially relevant for high-voltage designs where the dielectric spacing determines the breakdown voltage rating.
Finally, many designers forget to check the drill aspect ratio when they increase board thickness for mechanical rigidity. A 2.4 mm board with 0.15 mm vias has an aspect ratio of 16:1, which exceeds most standard manufacturing capabilities. Either increase the via size or reduce the board thickness to keep the aspect ratio within the manufacturer's limits.
Review Checklist for Your Multilayer Stackup
Before you send your Gerbers for fabrication, run through this checklist to catch stackup issues early. Each item addresses a common source of DFM rejection or assembly failure.
| Check Item | What to Verify | Why It Matters |
|---|---|---|
| Symmetry | Layer stackup is symmetric about the center line | Prevents warpage during lamination and reflow |
| Total thickness | 1.6 mm standard; matches available core/prepreg combos | Avoids forced stackup changes by manufacturer |
| Copper weight | Outer 1 oz, inner 0.5 oz for default; adjust for high current | Balances cost, impedance, and current capacity |
| Dielectric spacing | Matches target impedance; verify with manufacturer's materials | Ensures impedance tolerance is achievable |
| Reference planes | Solid plane under high-speed signals; no splits | Maintains return current path and signal integrity |
| Drill aspect ratio | Board thickness to smallest via ≤ 10:1 | Ensures reliable plating through vias |
| Impedance notes | Target impedance and tolerance stated for each net | Avoids ambiguity in fabrication and testing |
| Material selection | FR-4 for standard; low-loss for high-speed; high-Tg for thermal | Matches electrical and thermal requirements |
| Copper balance | Copper distribution is even across the cross-section | Reduces warp risk during reflow |
For a broader DFM perspective that covers routing, clearance, and component placement rules, review the PCB Design Guidelines for Beginners: Rules and DFM Checklist. If your design involves flexible sections, the material selection logic differs from rigid boards; see the Flex PCB Manufacturing Process: Materials Selection, Etching, & Lamination for the process differences, and the material guidance in How to Choose the Right Material for Your Flexible LED PCBs for flex-specific considerations.
Frequently Asked Questions
What is the default multilayer PCB stackup recommendation?
For most standard digital designs, use a symmetric 4-layer stackup with 1.6 mm total thickness, 1 oz copper on outer layers, 0.5 oz on inner layers, and FR-4 with a dielectric constant of about 4.2. This provides a solid power/ground plane pair and is cost-effective for fabrication. The symmetric arrangement prevents warpage, and the standard thickness matches common enclosure and connector requirements.
When should I change from the default stackup?
Change the stackup when you need controlled impedance, higher layer count, or specific dielectric materials. For RF or high-speed signals, select low-loss laminates and adjust the dielectric thickness to achieve target impedance. For high-current paths, increase copper weight on the relevant layers. If your assembly process uses lead-free solder with high reflow temperatures, consider a higher-Tg material for additional thermal margin.
What should I verify in the fabrication data for a multilayer stackup?
Check that the stackup drawing matches your layer order, dielectric materials, copper weights, and total thickness. Verify that the impedance requirements are clearly stated for each controlled-impedance net, and confirm that the drill file matches the via sizes and aspect ratios allowed by the manufacturer. Also confirm that the material specifications reference the correct IPC-4101 laminate grade for your application.
What should I ask my PCB manufacturer about stackup?
Ask for their standard stackup options and available dielectric thicknesses. Confirm whether they can meet your total thickness and impedance tolerance, and ask about copper balancing rules and minimum dielectric spacing for your layer count. Also ask about their drill aspect ratio limits and whether they provide impedance test coupons with the same stackup as your board. At Omini, we review stackup selections against our available materials and process capabilities during the DFM check to ensure your design is manufacturable as specified.