Direct Answer
Controlled impedance means the PCB is built so selected traces behave like transmission lines with a known characteristic impedance. It is not enough to label a net as 50 ohm or 100 ohm in the layout. The fabricator needs the layer, reference plane, copper thickness, dielectric thickness, laminate family, solder mask condition, target tolerance, and test requirement.
Start with the PCB Stack-Up and Signal Integrity for High-Speed Boards guide, then validate first-pass geometry with the PCB Impedance Calculator. Treat calculator output as a design estimate, not as fabrication authority.
Engineering Principles
Impedance is set by field geometry. A microstrip trace uses a plane below the trace as the main return path, while a stripline trace is embedded between reference planes. Width, copper thickness, dielectric height, dielectric constant, and solder mask all change the field distribution. Differential pairs add two more variables: spacing between the traces and the symmetry of the pair against nearby copper.
The manufacturing problem is variation. Laminate thickness has tolerance, etched copper width shifts from artwork, copper plating changes final thickness, and solder mask coverage can differ between outer layers. A robust design leaves margin for those variations instead of forcing the fabricator to hold a geometry at the edge of its process.
Practical Formula
There is no single closed-form equation that covers every PCB stackup, so use field-solver or calculator output for design work. The engineering relationship is still simple:
impedance = function(trace width, copper thickness, dielectric height, dielectric constant, solder mask, reference plane geometry)
For a worked estimate, assume an outer-layer single-ended trace needs 50 ohm impedance. If the preliminary calculator result says 0.18 mm width on a chosen dielectric thickness, do not freeze that width until the fabricator confirms actual prepreg, final copper thickness, and etch compensation. If the fabricator proposes 0.16 mm after CAM compensation, check spacing and loss again before approval.
Comparison Table
| Design choice | Best use | Main risk | Manufacturing note |
|---|---|---|---|
| Microstrip | Outer-layer RF, USB, Ethernet, display links | More exposed to solder mask and environment | Confirm whether solder mask is included in the impedance model |
| Stripline | Dense high-speed routing inside multilayer boards | Harder to probe and rework | Requires stable dielectric thickness above and below the trace |
| Loose tolerance | General digital interfaces with margin | May not protect a marginal channel | Lower cost and easier yield |
| Tight tolerance | High-speed links with small eye margin | Higher cost and more engineering queries | Needs clear coupon and test requirements |
Fabrication Release Checklist
Put impedance requirements in the fabrication drawing, not only in routing constraints. List each controlled structure by net class, layer, target impedance, tolerance, and reference plane. If the board has both single-ended and differential structures, separate them clearly. If the fabricator may adjust width to meet impedance, state the allowed adjustment range.
Do not mix a controlled impedance requirement with vague material notes such as "FR-4 or equivalent" when the channel has real margin limits. Equivalent materials can differ in dielectric constant, loss tangent, resin content, and thickness availability. The safer instruction is to specify the electrical target and let the fabricator propose a qualified stackup for approval.
Common Failure Modes
The most common failure is routing before stackup approval. A later dielectric change shifts impedance, and the layout must be widened or narrowed after placement is already crowded. Another failure is asking for tight impedance tolerance while also demanding the cheapest standard build. That conflict usually appears as a CAM question, a quote revision, or a delayed first article.
Controlled impedance also intersects with DFM. Very narrow traces, tight differential spacing, and edge-coupled pairs near copper pours can be electrically intentional but difficult to fabricate. Review these tradeoffs with Common DFM Issues and How to Avoid Them in PCB Design before sending Gerbers.
Related Omini Engineering Notes
- PCB manufacturing capabilities
- Cheap PCB Manufacturing: Common Mistakes That Kill Your Budget
- Decoding High-Density Interconnect (HDI) PCB Technology: An Overview