Direct Answer
A 4 layer PCB is manufactured by imaging and etching two inner copper layers, treating them with oxide, laminating them with prepreg and copper foil under heat and pressure, then drilling, plating, and patterning the. Outer layers to create interconnections. The process requires precise layer alignment, controlled impedance, and balanced copper distribution to prevent warpage and ensure reliable vias.
Why the 4 Layer PCB Structure Matters
The 4 layer PCB is the most common multilayer board used in industrial, automotive, and consumer electronics because it offers a practical balance between routing density, signal integrity, and cost. Unlike a 2 layer board, the 4 layer stackup provides dedicated reference planes for controlled impedance and noise reduction, which is essential for microcontrollers running at 100 MHz or higher, mixed-signal circuits, and power electronics with fast switching edges.
From a manufacturing perspective, the transition from 2 to 4 layers introduces the lamination step, which fundamentally changes how the board is built. A 2 layer board starts with a copper-clad laminate and only requires imaging, etching, drilling, and plating. A 4 layer board requires building the inner layers first, bonding them together, and then completing the outer layers. This added complexity affects yield, lead time, and cost, so understanding the process helps you design for manufacturability from the start.
For comparison, a Double Sided PCB: Advantages, Applications, and Manufacturing Process uses a simpler flow with no lamination, but it cannot provide the same power integrity or routing density as a 4 layer design.
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Standard 4 Layer Stackup and Material Selection
The Symmetric Stackup
A typical 4 layer stackup is:
| Layer | Function | Copper Weight |
|---|---|---|
| L1 (Top) | Signal / Component | 1 oz (35 µm) |
| L2 | Ground Plane | 1 oz (35 µm) |
| L3 | Power Plane | 1 oz (35 µm) |
| L4 (Bottom) | Signal / Component | 1 oz (35 µm) |
The core between L2 and L3 is typically 0.8 mm to 1.0 mm thick FR-4, while the prepreg layers between L1-L2 and L3-L4 are 0.2 mm to 0.3 mm each. The total finished thickness is usually 1.6 mm, which matches standard connector and enclosure specifications.
Symmetry is not optional. If the prepreg and core thicknesses are unbalanced, the board will bow or twist after lamination and again after reflow soldering. IPC-6012, which covers rigid PCB qualification and performance, includes flatness requirements that an unbalanced stackup will fail. When you specify your stackup, always mirror the copper weight and dielectric thickness around the center core.
Laminate Selection
FR-4 is the default choice for 4 layer boards because it is well-characterized, inexpensive, and available worldwide. For standard applications, specify FR-4 with a glass transition temperature (Tg) of 150°C to 170°C. If your board will undergo lead-free reflow at 245°C to 260°C peak, a Tg of 170°C provides better dimensional stability and reduces the risk of barrel cracks in vias.
For high-speed designs, the standard FR-4 dielectric constant (Dk) of approximately 4.2 to 4.5 at 1 GHz is often too lossy. In that case, specify a low-loss laminate such as Rogers 4350B or Isola FR408HR. However, these materials cost 3 to 5 times more than FR-4 and require different drilling parameters, so only use them when the signal integrity budget demands it. IPC-4101 defines the material specification system for base laminates, so reference it when you need to communicate exact material grades to your manufacturer.
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Step-by-Step Manufacturing Process
Step 1: Inner Layer Imaging and Etching
The process begins with a copper-clad laminate that has copper on both sides. This laminate is cleaned, coated with dry film photoresist, and exposed to UV light through a phototool or direct laser imaging system. The phototool defines the circuit pattern for L2 and L3.
After exposure, the board passes through a developer that removes unexposed photoresist, leaving the copper exposed where the circuit traces will be. The exposed copper is etched away using cupric chloride or alkaline ammonia etchant. The remaining photoresist is stripped, leaving the inner layer circuit pattern.
The critical parameter here is etch compensation. The etchant removes copper laterally as well as vertically, so traces come out narrower than the phototool pattern. For 1 oz copper, you can expect approximately 1 mil (25 µm) of etch per side. Your design should account for this by using trace widths that are at least 1 mil wider than the minimum required after etching.
Step 2: Oxide Treatment and Layer Alignment
Before lamination, the inner layers undergo an oxide or alternative oxide treatment. This creates a micro-roughened surface on the copper that improves adhesion between the copper and the prepreg resin. The treatment also prevents moisture from migrating along the copper-resin interface, which is a common cause of delamination and CAF (conductive anodic filament) failures.
After oxide treatment, the inner layers are stacked with prepreg sheets and outer layer copper foil. The stack is placed in a lamination press where an alignment system, typically using tooling pins or optical targets, ensures the layers are registered to each other. Misalignment of even 2 to 3 mils (50 to 75 µm) can cause annular ring violations on vias, so this step requires tight process control.
Step 3: Lamination
Lamination bonds the layers together under heat and pressure. The press applies 300 to 500 psi at 180°C to 200°C for 60 to 90 minutes, depending on the prepreg resin system and board thickness. During this cycle, the prepreg resin melts, flows, and cures, filling the gaps between the inner layer traces and bonding the copper foil to the stack.
The key risk during lamination is resin starvation or voids. If the prepreg does not have enough resin to fill the etched channels between traces, voids can form, which weaken the bond and create paths for moisture ingress. This is why balanced copper distribution matters: if one area of the board has large copper pours and another has sparse traces, the resin flow will be uneven. Your design should use copper thieving or cross-hatched pours in open areas to keep the copper density consistent across each layer.
Step 4: Drilling
After lamination, the board is drilled to create through-holes for vias and component leads. CNC drilling machines use carbide bits at 80,000 to 150,000 RPM. The drill bit size must account for the final plated hole diameter: the drilled hole is typically 3 to 4 mils larger than the finished hole to allow for copper plating.
For a 1.6 mm thick 4 layer board, the aspect ratio (board thickness divided by hole diameter) should not exceed 10:1 for reliable plating. A 0.2 mm finished via requires a 0.24 mm drill, giving an aspect ratio of approximately 6.7:1, which is within standard capability. If you need smaller vias, consider laser-drilled microvias, but these require a sequential lamination process that significantly increases cost.
Step 5: Electroless Copper and Panel Plating
The drilled holes are non-conductive, so they must be plated to connect the layers. The board first goes through an electroless copper bath that deposits a thin layer (0.5 to 1 µm) of copper on the hole walls. This is followed by panel plating, which builds up the copper thickness to approximately 5 to 8 µm.
The electroless process is sensitive to contamination. If the drilled hole walls have resin smear from the drilling process, the copper will not adhere properly. A desmear step using permanganate or plasma etching removes the smear before plating. This is especially important for high-Tg materials, which tend to smear more than standard FR-4.
Step 6: Outer Layer Imaging and Etching
The outer layers are now processed similarly to the inner layers. Dry film photoresist is applied, exposed, and developed. The exposed copper is plated with additional copper and then with tin or tin-lead, which acts as an etch resist. The photoresist is stripped, and the bare copper is etched away, leaving the plated traces and pads.
The outer layer etch process is more challenging than the inner layer because the traces must be etched around the plated through-holes. The plating adds thickness to the trace tops, which can cause undercutting if the etch time is too long. This is why outer layer trace and space requirements are typically larger than inner layer requirements—most manufacturers recommend 5/5 mil trace/space minimum for outer layers versus 4/4 mil for inner layers.
Step 7: Solder Mask and Silkscreen
Solder mask is applied to protect the copper from oxidation and prevent solder bridges during assembly. The two main methods are liquid photoimageable solder mask (LPI) and dry film. LPI is applied by curtain coating or spray, then exposed and developed to open the pads. The solder mask thickness over traces is typically 10 to 20 µm, and the registration tolerance is ±2 to 3 mils.
Silkscreen is applied after solder mask. It is used for reference designators, polarity marks, and assembly instructions. The minimum line width for silkscreen is 4 to 5 mils, and it should never be placed on exposed pads because it can interfere with soldering.
Step 8: Surface Finish
The surface finish protects the exposed copper pads from oxidation and provides a solderable surface. The most common finishes are:
| Finish | Thickness | Best For | Cost |
|---|---|---|---|
| HASL (lead-free) | 1-25 µm | General purpose, low cost | Low |
| ENIG | 3-6 µm Ni + 0.05-0.1 µm Au | Fine pitch, flat pads | Medium |
| OSP | 0.2-0.5 µm | Solderability, no lead | Low |
| Immersion Silver | 0.15-0.3 µm | High frequency, wire bonding | Medium |
For fine-pitch components (0.4 mm or smaller), ENIG is preferred because it provides a flat surface. HASL can leave uneven surfaces that cause solder paste stencil printing issues. OSP is cost-effective but has a shorter shelf life and requires careful handling.
Step 9: Electrical Testing and Final Inspection
The finished board undergoes electrical testing to verify continuity and isolation. Flying probe testing is used for low-volume production, while fixture-based testing is faster for high-volume runs. The test fixture contacts every net on the board and checks for shorts and opens.
Final inspection includes automated optical inspection (AOI) for solder mask and silkscreen quality, and a cross-section analysis on a sample board to verify plating thickness, layer alignment, and dielectric thickness. If you specified impedance control, the manufacturer should provide a coupon test report showing the measured impedance values.
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Design for Manufacturability Best Practices
Balanced Copper Distribution
Uneven copper distribution is the most common cause of 4 layer PCB warpage. When one area of the board has a solid copper pour and another has only traces, the laminate cools at different rates, causing internal stress. Use cross-hatched pours (typically 70% fill) in large open areas to balance the copper density. This also reduces the amount of copper that must be etched, which shortens etch time and improves dimensional stability.
Panel Utilization
A standard panel size is 18 × 24 inches (457 × 610 mm). Your board should be designed so that multiple units fit efficiently on the panel with minimal waste. A rectangular board with dimensions that divide evenly into the panel is more cost-effective than an odd-shaped board. For example, a 100 × 80 mm board fits 12 units on a standard panel, while a 105 × 85 mm board fits only 9 units, increasing the per-board cost by approximately 25%.
Via Placement and Annular Ring
Vias should be spaced at least 0.5 mm apart to prevent thermal damage during drilling. The annular ring (the copper pad surrounding the drilled hole) should be at least 4 mils for outer layers and 3 mils for inner layers. If the annular ring is too small, drill misalignment can cause the hole to break out of the pad, creating a reliability risk.
Minimum Trace and Space
Check your manufacturer's capability before finalizing your design. Most standard manufacturers can produce 4/4 mil trace and space on inner layers and 5/5 mil on outer layers. If you need tighter tolerances, expect higher cost and lower yield. A good rule of thumb is to use the largest trace and space that your design allows, not the smallest that the manufacturer can produce.
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Common Mistakes and How to Avoid Them
Mistake 1: Ignoring the Stackup Drawing
Many engineers provide only Gerber files without a stackup drawing. This forces the manufacturer to guess at the layer order and dielectric thickness, which can result in incorrect impedance and unexpected board thickness. Always provide a stackup drawing that includes layer order, material type, copper weight, dielectric thickness, and impedance requirements.
Mistake 2: Not Running a DFM Check
Before sending files to fabrication, run a DFM check using your EDA tool or a third-party service. This catches issues like insufficient clearances, annular ring violations, and missing drill files. A DFM check takes minutes but can save days of rework.
Mistake 3: Specifying Unnecessary Requirements
Specifying IPC-6012 Class 3 when Class 2 would suffice increases cost without adding value. Class 3 is for high-reliability applications like aerospace and medical devices, where failure is not an option. If your product is consumer electronics, Class 2 is appropriate. Be honest about your reliability requirements and let the manufacturer quote accordingly.
Mistake 4: Forgetting About Impedance Control
If your design has high-speed signals, specify impedance control in your RFQ. The manufacturer will need to adjust the trace widths and dielectric thickness to hit your target impedance, which may require a different stackup than your initial design. Provide the target impedance values and the tolerance (±10% is standard, ±5% is tighter and more expensive).
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Practical Example: A Mixed-Signal 4 Layer Board
Consider a data acquisition board with a 16-bit ADC, an FPGA, and a USB 3.0 interface. The stackup is:
- L1: Signal (1 oz) — ADC inputs, FPGA routing, USB differential pairs
- L2: Ground (1 oz) — solid ground plane, no splits
- L3: Power (1 oz) — split into 3.3V, 1.8V, and 5V islands
- L4: Signal (1 oz) — component placement, decoupling caps
The USB 3.0 differential pairs require 85Ω differential impedance. The manufacturer adjusts the L1-L2 dielectric thickness to 0.2 mm and the trace width to 5 mils with 8 mil spacing to achieve this. The ADC analog inputs are routed on L1 with a ground guard trace to isolate them from the digital FPGA signals.
During the DFM review, the manufacturer flags that the 0.2 mm via drill size is too small for the 1.6 mm board thickness (aspect ratio 8:1, which is borderline). The design is revised to use 0.25 mm vias, which improves plating reliability without affecting the routing.
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When to Involve the Manufacturer
Involve your manufacturer early, ideally during the stackup selection phase. Provide your layer count, board thickness, impedance requirements, and component density, and ask for their recommended stackup. They will know which prepreg and core combinations are in stock and which are cost-effective.
For complex designs, request a cross-section report after the first prototype run. This verifies the actual layer thicknesses, copper weights, and via plating quality. Compare this to your stackup drawing to confirm the manufacturer followed your specifications.
If you are designing a flexible circuit, the process differs significantly. See our Flex PCB Manufacturing Process: An Overview for Beginners for details on polyimide materials and dynamic flexing considerations. For high-power applications, our Guidelines for Metal Core PCB Design: Best Practices & Tips covers aluminum and copper core boards that improve thermal dissipation.
If you are planning to scale to a Guide To Six-Layer PCB Stack-up and Manufacturing Process, the same principles apply, but the lamination process becomes more complex with additional layers. And once your board is fabricated, the Explained: What are the Steps in SMT Assembly Process? guide explains how your 4 layer board moves through stencil printing, component placement, and reflow soldering.
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Frequently Asked Questions
Why is a 4 layer PCB preferred over a 2 layer PCB for many designs?
A 4 layer PCB provides dedicated power and ground planes, which reduces noise and improves signal integrity. The planes also act as reference planes for controlled impedance traces, which is essential for high-speed interfaces. Additionally, the extra routing layers reduce the need for wire jumpers and reduce electromagnetic interference.
What is the typical stackup for a 4 layer PCB and why is symmetry important?
The typical stackup is signal/ground/power/signal. Symmetry is critical because an unbalanced stackup causes the board to warp during lamination and reflow soldering. The mechanical stress from uneven copper and dielectric thickness can cause the board to bow or twist, leading to assembly issues and solder joint failures.
How do I verify my 4 layer PCB stackup before fabrication?
Provide a complete stackup drawing with layer order, material type, dielectric thickness, copper weight, and impedance requirements. Ask the manufacturer for a cross-section report after fabrication to confirm actual layer thicknesses and alignment. This report should show the plated through-hole cross-section and the layer-to-layer registration.
What are the common mistakes in 4 layer PCB design that affect manufacturability?
Common mistakes include unbalanced copper distribution, excessive via density in one area, insufficient annular ring, and ignoring minimum trace and space capabilities. Failing to plan for panel utilization also increases cost unnecessarily. Run a DFM check before sending files to fabrication.
What information should I include in an RFQ for a 4 layer PCB?
Include layer count, board dimensions, material type (e.g., FR-4 Tg170), copper weight per layer, surface finish, solder mask color, silkscreen requirements, impedance specifications, and IPC class. Provide Gerber files, drill files, and a stackup drawing. If you have special requirements like controlled impedance or blind vias, state them explicitly.
How does the manufacturing process of a 4 layer PCB differ from a 2 layer PCB?
The main difference is the lamination step, where inner layers are bonded with prepreg and copper foil under heat and pressure. This requires precise alignment and oxide treatment of inner layers. Drilling and plating are similar but must account for the thicker board and the need for reliable interlayer connections. The 4 layer process also requires more careful thermal management during lamination to prevent warpage.
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At Omini, we work with engineers to optimize 4 layer PCB designs for manufacturability, providing stackup recommendations and DFM feedback before fabrication begins. Contact our engineering team with your design files to get a manufacturability review and a quote tailored to your volume and reliability requirements.
> Engineering handoff note: Manufacturing Techniques for High-Frequency PCBs: A Deep Dive before the release package is frozen.