Direct Answer
The most common PCB defects fall into three categories: fabrication flaws in the bare board, solder and placement issues introduced during assembly, and latent defects that only appear under electrical load or environmental stress. Identifying them requires matching the right inspection method to each defect type—visual and AOI for surface solder problems, electrical test for opens and shorts, and X-ray or cross-section for hidden structural faults. Caught early, these defects are manageable; missed, they become yield killers, schedule delays, and warranty claims.
Fabrication Defects in the Bare Board
Fabrication defects originate in etching, lamination, drilling, and plating. They exist before any component touches the board, which makes pre-assembly inspection critical for protecting downstream value.
Opens and Shorts
Opens occur when a trace is interrupted, a pad is lifted, or a via barrel fails to plate through. Shorts happen when excess copper bridges two nets, often from under-etching or photoresist defects. Both are caught reliably with electrical test—flying probe for prototypes and small lots, bed-of-nails ICT for volume. A good fabricator will run 100% netlist verification on production boards. If your supplier skips this or charges extra, that is a red flag.
Plating Voids and Barrel Cracks
Plated through-holes (PTHs) and microvias carry current between layers. When plating is thin or discontinuous, the barrel may crack under thermal cycling or fail to conduct at all. These defects are invisible to AOI. Cross-sectional analysis at coupon level, or microsectioning of suspect boards, reveals plating thickness and barrel integrity. For high-reliability applications—automotive, aerospace, medical—require IPC Class 3 plating minimums and demand microsection data on first articles.
Layer Misregistration and Del PCB Stackup Problems
Multilayer boards depend on precise layer-to-layer alignment. Misregistration causes drilled vias to miss capture pads, creating opens or weakened connections. Delamination separates layers under thermal stress, often from inadequate cure, moisture ingress, or excessive thermal shock during lead-free reflow. Both defects require cross-section and sometimes thermal stress testing to detect. A disciplined PCB Stack-Up and Signal Integrity for High-Speed Boards review during design prevents the geometric conditions that lead to these failures.
Surface Finish Issues
ENIG, HASL, OSP, and immersion tin each carry distinct defect risks. ENIG can suffer black pad syndrome—brittle nickel-phosphorus layers that fracture under solder stress. HASL creates uneven thickness that challenges fine-pitch components. OSP degrades with time and thermal exposure. Inspect finish uniformity under magnification, verify thickness with XRF, and track shelf life strictly. Omini manages finish selection against component mix and reflow profile to avoid these pitfalls on customer programs.
Assembly-Induced Defects
Assembly introduces solder, placement, and handling defects. The cost to find these rises sharply the later they are caught—a bad joint on a $0.03 resistor is cheap to rework; the same defect under a $400 FPGA is not.
Solder Bridging and Insufficient Solder
Bridging forms when excess solder connects adjacent pins or pads, usually from stencil aperture oversize, poor paste release, or a misaligned screen print. Insufficient solder creates weak or open joints from clogged apertures, low paste volume, or inadequate reflow time. AOI catches both at line speed. The root cause, however, is upstream: stencil design, printer setup, and reflow profile. Reviewing Common DFM Issues and How to Avoid Them in PCB Design before releasing Gerbers eliminates many of these variables.
Tombstoning and Component Shift
Tombstoning pulls a passive component vertical when one pad wets before the other, often from uneven heating, pad geometry imbalance, or paste volume mismatch. Component shift occurs when parts move during reflow from paste tackiness loss or excessive vibration. Both affect yield and, in severe cases, cause electrical shorts. Reflow profiling with thermocouples on actual product, not just a generic recipe, prevents these issues. For high-mix, low-volume shops, this discipline separates reliable EMS providers from commodity assemblers.
BGA and Hidden Joint Defects
BGA, QFN, and other bottom-terminated packages hide their solder joints from optical inspection. Voids, insufficient solder, and misalignment require X-ray inspection to detect. Void standards vary by application—IPC allows up to 25% voiding for general electronics, but automotive and aerospace programs often demand 10% or less. AOI and X-Ray Inspection in PCB Assembly explains how these methods complement each other for complete coverage.
Component Damage and Polarity Errors
ESD mishandling, excessive pick-and-place force, and incorrect feeder setup can damage sensitive components or place them with reversed polarity. These defects slip past electrical test if the damage is latent or the polarity error does not create an immediate short. Incoming component inspection, proper MSD handling, and first-article verification of placement programs reduce incidence.
Latent and Field-Failure Defects
The most expensive defects are those that pass factory test and fail in the field. They stem from design margin, material selection, or process control gaps that only manifest under stress.
Electrochemical Migration and Dendritic Growth
When ionic residues from flux, handling, or plating chemistry remain on the board, moisture and bias voltage drive metal migration between conductors. Over time, this creates dendrites that bridge gaps and cause intermittent shorts. Cleanliness testing per IPC-TM-650, ion chromatography, and proper baking before conformal coating all help prevent this. The defect is invisible at shipment and may take months to fail.
CAF and Insulation Resistance Degradation
Conductive Anodic Filament (CAF) growth occurs when moisture and voltage bias drive copper migration along glass fiber interfaces in the laminate. It creates high-resistance shorts between layers or along edges. CAF resistance depends on laminate material, hole-to-hole spacing, and environmental exposure. High-reliability designs use CAF-resistant materials and maintain adequate spacing between PTHs in the same potential field.
Thermal Cycling and Fatigue Failures
CTE mismatch between laminate, copper, and components generates stress during temperature swings. Over cycles, this stress cracks vias, lifts pads, and fractures solder joints. Heavy copper designs are especially vulnerable because the copper itself drives CTE imbalance. Understanding Common Failures in Heavy Copper PCB and How to Avoid Them in the Design Stage helps engineers specify appropriate via structures, anchor patterns, and thermal relief before fabrication commits.
Practical Identification Workflows
Effective defect identification matches the method to the risk, not just the available equipment.
| Defect Category | Primary Detection | Secondary Verification | When to Apply |
|---|---|---|---|
| Opens/Shorts | Flying probe / ICT | Visual trace follow | 100% on bare board and loaded assembly |
| Solder bridging | AOI | Manual microscope | Every board post-reflow |
| BGA voids, misalignment | X-ray | Cross-section on samples | First article, process change, or complaint |
| Plating voids, barrel cracks | Cross-section | SEM/EDX if root cause unclear | First article, quarterly process audit |
| Delamination, CAF | Thermal stress + cross-section | Insulation resistance testing | Material qualification, field failure return |
| Ionic contamination | Ion chromatography | SIR testing | High-reliability or outdoor applications |
Preventing Defects Through Design and Process Control
The majority of PCB defects are preventable before the first panel is processed. A rigorous DFM review catches pad geometry errors, insufficient clearances, and unmanufacturable aspect ratios. Material selection—standard FR-4, high-Tg, low-Dk, or metal-backed—must match the thermal and mechanical environment. And process control at the fabricator and assembler, documented with SPC data, provides the consistency that prevents drift into defect territory.
Buyers evaluating suppliers should ask for first-article inspection data, process capability indices for critical dimensions, and corrective action records from recent escapes. Cheap PCB Manufacturing: Common Mistakes That Kill Your Budget details how lowest-bidder sourcing often sacrifices exactly these controls, converting apparent savings into rework and delay costs.
Omini integrates DFM feedback, incoming material verification, and in-process inspection across its PCB fabrication and EMS lines. This closed-loop approach catches defects at the stage where correction is still economical—typically design review or first article—rather than in customer incoming inspection or, worse, end-user hands. For programs where reliability and schedule certainty matter more than marginal unit cost, that integration is the difference between a supplier and a manufacturing partner.